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[Software EngineeringDJDPLV_LWB

Description: 利用超高速硬件描述语言(VHDL)在现场可编程逻辑门阵列(FPGA)上编程实现的纯数字式等精度频率计,不但具有较高的测量精度,而且其测量精度不会随着被测信号频率的降低而下降。为了实现对任意信号进行频率测量,在前端输入加整形电路即可。-use ultra-high-speed Hardware Description Language (VHDL) in field programmable logic gate array (FPGA) series The way to achieve such pure digital frequency meter accuracy, not only with higher measurement accuracy, but not its measurement precision frequency signals measured with the decrease. In order to achieve the arbitrary measurement signal frequency, increase input in the front plastic circuit can be.
Platform: | Size: 30945 | Author: 刘刚 | Hits:

[VHDL-FPGA-Verilogpinlvji

Description: 基于FPGA的数字频率计,超大范围测量,误差非常之小,内含详细程序-FPGA-based digital frequency meter super scope of measurement, the error is very small, containing detailed procedures
Platform: | Size: 45056 | Author: 刘嵘 | Hits:

[Software EngineeringDJDPLV_LWB

Description: 利用超高速硬件描述语言(VHDL)在现场可编程逻辑门阵列(FPGA)上编程实现的纯数字式等精度频率计,不但具有较高的测量精度,而且其测量精度不会随着被测信号频率的降低而下降。为了实现对任意信号进行频率测量,在前端输入加整形电路即可。-use ultra-high-speed Hardware Description Language (VHDL) in field programmable logic gate array (FPGA) series The way to achieve such pure digital frequency meter accuracy, not only with higher measurement accuracy, but not its measurement precision frequency signals measured with the decrease. In order to achieve the arbitrary measurement signal frequency, increase input in the front plastic circuit can be.
Platform: | Size: 30720 | Author: 刘刚 | Hits:

[VHDL-FPGA-Veriloggwdvpb

Description: 利用等精度测量原理,通过FPGA运用VHDL编程设计一个数字式频率计 设计具有较高的实用性和可靠性-The use of precision measuring principle, the use of VHDL programming through the FPGA to design a digital frequency meter design with high practicality and reliability of
Platform: | Size: 1024 | Author: tangjia | Hits:

[Embeded-SCM Developvb

Description: A digital fi‘equeney meter designed with FPGA development software Q-~us 11 is introduced.The 1 Hz—l MHz input measured pulse signals of the digital ii‘equency meter can be used for measuring frequency,period,pulse width and duty ratio,etc.The test results stably display O71 3 seven—segment numeric tubes,and the measuring ranges may be switched over automatically.The measuring error is equal to or less than 0.1%. -A digital fi equeney meter designed with FPGA development software Q-~ us 11 is introduced. The 1 Hz-l MHz input measured pulse signals of the digital ii equency meter can be used for measuring frequency, period, pulse width and duty ratio, etc. The test results stably display O71 3 seven-segment numeric tubes, and the measuring ranges may be switched over automatically. The measuring error is equal to or less than 0.1.
Platform: | Size: 192512 | Author: | Hits:

[VHDL-FPGA-Verilogfrequence

Description: 基于FPGA设计的数字频率计,用VHDL写的代码。。。。有6各模块-FPGA-based design of digital frequency meter, use VHDL to write code. . . . Each module has 6
Platform: | Size: 2048 | Author: 张新福 | Hits:

[assembly languageeda

Description: 课程设计要求设计并用FPGA实现一个数字频率计,功能:频率计。具有4位显示,能自动根据7位十进制计数的结果,自动选择有效数据的-Curriculum design to design and FPGA implementation of a digital frequency meter, function: frequency meter. With four shows that will automatically count 7 the results of the metric system, automatic selection of effective data
Platform: | Size: 2293760 | Author: 崔晓进 | Hits:

[VHDL-FPGA-VerilogFPGA

Description: 基于FPGA的数字频率计的设计11利用VHDL 硬件描述语言设计,并在EDA(电子设计自动化) 工具的帮助下,用大规模可编程逻辑器件(FPGA/ CPLD) 实现数字频率计的设计原理及相关程序-FPGA-based design of digital frequency meter 11, the use of VHDL hardware description language design, and EDA (electronic design automation) tools with the help of large-scale programmable logic devices used (FPGA/CPLD) digital frequency meter and the design principle related procedures
Platform: | Size: 665600 | Author: 董晨晨 | Hits:

[VHDL-FPGA-Verilogdengjingdu

Description: 根据第三届(1997年)全国大学生电子设计竞赛题目:简易数字频率计,完全用FPGA芯片做的一个等精度数字频率计。-According to the third (1997) National Undergraduate Electronic Design Contest Topic: simple digital frequency meter, complete with a FPGA chip, such as doing precision digital frequency meter.
Platform: | Size: 3051520 | Author: song | Hits:

[VHDL-FPGA-Verilogfreq_counter(Verilog)

Description: 数字频率计FPGA代码,用verilog语言实现。-Digital frequency meter FPGA code with verilog language.
Platform: | Size: 435200 | Author: 郭志东 | Hits:

[VHDL-FPGA-Verilogfsh

Description: 这是我的毕业可用8位的LED显示,有小数点的。设计哦,可以用的。可供参考-VHDL-based digital frequency meter With the rapid development of electronic technology, FPGA/CPLD appear in its high-speed, high reliability, series parallel mode of outstanding merit widely used in the electronic design, and EDA design represents the future direction. In this paper, based on the principle of equal precision frequency meter measuring frequency is a typical application. Through the FPGA using VHDL hardware description programming language, in addition to the plastic part of the measured signal, key input part and the digital display part, the rest all in one FPGA chip implementation, such as 8-bit digital precision frequency meter. Using Quartusll integrated development environment for editing, synthesis, wave simulation, and download to the FPGA, by the actual circuit testing. And other precision frequency meter has high availability and reliability, high precision, and accuracy varies with frequency. System frequency measurement range of up to 0-25MHz, the frequency m
Platform: | Size: 4354048 | Author: 战魔 | Hits:

[VHDL-FPGA-VerilogDigital-frequency

Description: 数字频率计,可用来测试和输出相应频率。使用C51单片机和FPGA实现。-Digital frequency meter, used to test and output the corresponding frequency. With C51 MCU and FPGA.
Platform: | Size: 2048 | Author: | Hits:

[VHDL-FPGA-Verilogcounter

Description: 本文介绍了基于FPGA的数字频率计的设计方法,设计采用硬件描述语言Verilog ,在软件开发平台ISE上完成,可以在较高速时钟频率(48MHz)下正常工作。该数字频率计采用测频的方法,能准确的测量频率在10Hz到100MHz之间的信号。-This article describes the FPGA-based digital frequency meter design method using hardware description language Verilog, ISE on the complete software development platform, can be compared with high-speed clock frequency (48MHz) to work properly. The digital frequency meter using frequency measurement method, can accurately measure the frequency of the signal between 10Hz to 100MHz.
Platform: | Size: 1880064 | Author: PengJ | Hits:

[VHDL-FPGA-VerilogFrequency-meter

Description: 用FPGA实现数字频率计,有数字显示功能-With FPGA realizing digital frequency plan, a digital display function
Platform: | Size: 1090560 | Author: 覃祖枢 | Hits:

[SCMmsp430

Description: 该源文件以msp430f149为CPU,内含MSP430各分模块的程序,适合单片机初学者学习,还有简易频率计,数字存储示波器,函数信号发生器三个模块的源程序,适合msp430学习者的实践。还带有FPGA的学习部分 含AD/DA-Msp430f149 the source file for the CPU, the sub-module containing MSP430 program for the microcontroller for beginners to learn, and simple frequency meter, digital storage oscilloscope, function generator three modules source code of practice for learners msp430 . Also with the learning part of the FPGA with AD/DA
Platform: | Size: 21143552 | Author: | Hits:

[VHDL-FPGA-Verilogfpga--pinlvji

Description: 基于fpga的数字频率计,才用等精度原理设计,编程用的是VHDL语言-Fpga-based digital frequency meter, only with the accuracy of the principle of design, programming with VHDL language
Platform: | Size: 246784 | Author: dongsir | Hits:

[VHDL-FPGA-VerilogFPGA

Description: 基于FPGA的数字频率计的课程设计,附完整代码。-FPGA-based digital frequency meter course design, with complete code.
Platform: | Size: 230400 | Author: 姚华 | Hits:

[VHDL-FPGA-Verilogquartus_works_second

Description: 基于verilog语言的,FPGA程序,实现频率计与数码管显示功能,转换频率48M,精度1Hz,量程1Hz~9999Hz,有欠频率和超频率提示,精度与量程可随外部设备改变而改变,在EP1C3T100C8上亲测通过-Based verilog language, FPGA procedures to achieve frequency meter with digital display, switching frequency 48M, precision 1Hz, range 1Hz ~ 9999Hz, frequency and ultra-frequency tips lacks accuracy and range can vary with changes in the external device, in EP1C3T100C8 measured by the pro-
Platform: | Size: 4190208 | Author: FT_Young | Hits:

[Otherpinlvji

Description: 一个用verilog编写的数字频率计,利用FPGA实现计数功能,其中使用的测周法。-A written with verilog digital frequency meter, use FPGA implementation counting function, wherein the measured circumference method to use.
Platform: | Size: 22528 | Author: 王哲 | Hits:

[VHDL-FPGA-VerilogFPGA-high-precision-frequency-meter

Description: 基于FPGA的高精度频率计设计实验 展示数字存储示波器基本工作原理。 展示硬件测频和测周的基本原理。 在现有综合实践平台上开发DSO硬件频率计模块的方案及流程。 结合数据采集、存储和触发模块的FPGA代码。 FPGA代码完善DSO的频率计模块,实现高精度测频和测周功能。-FPGA-based high-precision frequency meter design experiments       Demonstrate the basic working principle of digital storage oscilloscope.       Demonstrate the basic principles of frequency measurement and test hardware week. Developed on an existing platform integrated practice DSO hardware frequency counter module programs and processes. Combined with data collection, storage and trigger module FPGA code. FPGA code to improve DSO frequency meter module, high-precision frequency measurement and measurement capabilities week.
Platform: | Size: 14547968 | Author: liu | Hits:
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